1. Field of the Disclosure
The present disclosure relates to a semiconductor device including an active fin.
2. Description of the Related Art
A multi-gate transistor has been suggested as one possible scaling technique for increasing the density of a semiconductor device in which a multi-channel active pattern (or a silicon body) having a fin or nanowire shape is formed on a substrate and a gate is formed on a surface of the multi-channel active pattern.
Because such a multi-gate transistor uses three-dimensional channels, it is generally easy to perform the scaling. Further, even if a gate length of the multi-gate transistor is not increased, it is possible to improve the current control capability. Furthermore, it is possible to effectively suppress a short channel effect (SCE) in which the potential of the channel region is influenced by the drain voltage.